AT87251G2D-3CSUM【PDF 29/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

Table 28.

Summary of Exchange, Push and Pop Instructions

Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

3. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

Exchange bytesXCH A, <src>(A)

src opnd

Exchange DigitXCHD A, <src>(A)3:0 src opnd3:0

PushPUSH <src>(SP)

← (SP) +1; ((SP)) ← src opnd;

(SP)

← (SP) + size (src opnd) - 1

PopPOP <dest>(SP)

← (SP) - size (dest opnd) + 1;

dest opnd

← ((SP)); (SP) ← (SP) -1

Mnemonic

<dest>,

<src>(1)

Comments

Binary Mode

Source Mode

Bytes

States

Bytes

States

XCH

A, Rn

ACC and register

A, dir8

ACC and direct address (on-chip

RAM or SFR)

23(3)

A, at Ri

ACC and indirect address

XCHD

A, at Ri

ACC low nibble and indirect address

(256 bytes)

PUSH

dir8

Push direct address onto stack

2(2)

22(2)

#data

Push immediate data onto stack

#data16

Push 16-bit immediate data onto

stack

Push byte register onto stack

WRj

Push word register onto stack

DRk

Push double word register onto

stack

POP

dir8

Pop direct address (on-chip RAM or

SFR) from stack

23(2)

Pop byte register from stack

WRj

Pop word register from stack

DRk

Pop double word register from stack

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